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ADT7473
Table 60. REGISTER 0X37 ? DYNAMIC T MIN CONTROL REGISTER 2 (POWER-ON DEFAULT = 0X00) (Note 1)
Bit No.
<2:0>
<5:3>
<7:6>
Mnemonic
CYR1
CYL
CYR2
R/W
R/W
R/W
R/W
Description
3-bit Remote 1 cycle value. These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the Remote 1 channel, in terms of
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
Bits
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
3-bit Local temperature cycle value. These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the local temperature channel, in terms
of number of monitoring cycles. The system has associated thermal time constants that need
to be found to optimize the response of fans and the control loop.
Bits
Decrease Cycle
Increase Cycle
000
8 cycles (1 sec)
16 cycles (2 sec)
001
16 cycles (2 sec)
32 cycles (4 sec)
010
32 cycles (4 sec)
64 cycles (8 sec)
011
64 cycles (8 sec)
128 cycles (16 sec)
100
128 cycles (16 sec)
256 cycles (32 sec)
101
256 cycles (32 sec)
512 cycles (64 sec)
110
512 cycles (64 sec)
1024 cycles (128 sec)
111
1024 cycles (128 sec)
2048 cycles (256 sec)
2 LSBs of 3-bit Remote 2 cycle value. The MSB of the 3-bit code resides in Dynamic T MIN
Control Register 1 (Register 0x36). These three bits define the delay time between making
subsequent T MIN adjustments in the control loop for the Remote 2 channel, in terms of
number of monitoring cycles. The system has associated thermal time constants that need to
be found to optimize the response of fans and the control loop.
Bits Decrease Cycle Increase Cycle
000
001
010
011
100
101
110
111
8 cycles (1 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
16 cycles (2 sec)
32 cycles (4 sec)
64 cycles (8 sec)
128 cycles (16 sec)
256 cycles (32 sec)
512 cycles (64 sec)
1024 cycles (128 sec)
2048 cycles (256 sec)
1. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 61. MAXIMU M PWM DUTY CYCLE REGISTERS (POWER-ON DEFAULT = 0XFF) (Note 1, 2, and 3)
Register Address
0x38
0x39
0x3A
R/W (Note 2)
R/W
R/W
R/W
Description
Maximum Duty Cycle for PWM1 Output, Default = 100% (0xFF)
Maximum Duty Cycle for PWM2 Output, Default = 100% (0xFF)
Maximum Duty Cycle for PWM3 Output, Default = 100% (0xFF)
1. These registers set the maximum PWM duty cycle of the PWM output.
2. These registers become read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.
3. If Bit 3 of Configuration Register 4 (0x7D) is set, then on a THERM overtemperature event, fans go to their maximum programmed PWM value
as programmed here. If Bit 3 of Configuration Register 4 (0x7D) is 0, then on a THERM overtemperature event, fans go to 100% PWM.
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